Once again, here are some things I learned at this year's IWLPC show 2010 in Santa Clara. Picture below taken at Philadelphia airport, where I drafted this blog posting.
I think there could be ten things this time, but who’s counting?
- TSV stands for “through-silicon via”. AND “through-substrate via”. AND (as one attendee joked) “through-stuff via”. It’s also 2-3 years away from commercial implementation on anything other than camera modules: which I thought I heard last year. Hmmmm… Speaking of which…
- Camera modules are still the only commercial TSV applications at the moment, although I heard arguments that camera modules were not true TSV as either they “weren’t leveraging the real potential of TSV”: simply metal-lined apertures contacting the CCD pixels on the backside of the camera die. So more like “into-silicon vias” (ISV’s) than strictly through them.
- One of the major advantages of 3D stacking is heterogeneous system integration: you can put silicon, SOI, GaAs, MEMS etc all in one stack or some SiP-on-chip array and repartition the chip functionality in three dimensions exactly as you need it. You can also mix joining technologies together: coined metal bumps and ACF with diffusion bonding etc. Dr Peter Ramm of the newly renamed Fraunhofer EMFT gave a fascinating talk on the eCUBE and (new) eBRAINS projects. Peter also confessed that the eBRAINS acronym was a bit of a stretch, and I’m sure the desire for improved technology came before the acronym.
- Thermal management issues for 3D (TSV-based) memory will be less of an issue than previously thought, since the driver for memory integration is reduced power consumption. That’s either 40% or 50% reduction, depending on who you talk to. Fewer RC losses = lower power wastage; less heat. Boom: you’re done. Dr Bradley McCredie of IBM pointed out in his keynote speech that by moving to TSV for DRAM, you may get a significant power saving, but this doesn’t scale: once you’ve stacked the die, that’s it. One time offer, and then as the vias get thinner – the problem starts again.
- No surprise, but known good die (KGD) will be critical for chip-stacking, echoing Peter Ramm’s comments about testing for KGD. Unfortunately there are two issues here: 1/ (from Peter Ramm) that test pads will need to be integrated into the design, consuming real-estate that you thought you just won back 2/ That via-middle or via-last technology TSV will put added stresses on die that WERE KGD, up to the point that you put holes in them.
- The new paradigm for consumer devices is clearly “mobility, customizability and cooooolness (MCC)”. Sorry to seem preachy here, but I heard one marketing expert, and even one engineer trot out the old adage of “smaller / cheaper / faster” (SCF), which I hoped had died out around the end of the last century. The lesson from Apple’s iPAD (at time of writing reportedly selling 1-2million units a month) seems clear: consumers will pay for MCC no matter what. So how’s that SCF mantra working out for ya? The iPAD is much bigger than a cellphone; it’s priced at top dollar and is (arguably) not as functional as a laptop. SCF is rapidly becoming the Holy Roman Empire of marketing jibber-jabber. Ok: I think I’ve made my point: tell me what you think.
- As I said during the final WLP session I never thought I’d hear the words “Intel, wirebond and leadframe” used in the same sentence. Well, that was simply showing the depths of my ignorance. Dr Saeed Shojaie from Intel’s NAND Solutions Group in Fulsom, CA and his team have been working with PTI, using mixed diameter gold wire bonds (thus eliminating wire sweep) to allow stacking of 8 die or more on a leadframe: then mounting that stack-up inside something that looks awfully like a gull-wing LSOP (large scale outline package). OK: it IS a gull-wing LSOP. But it’s Intel, so it’s not your grandfather’s LSOP. They have done some interesting work on double-bends (“downset”) of the leads to eliminate distortion of the very delicate leadframe and still maintain the desired lead length.. Ok, you cry “Why not a TSV? They’re so cool!! “ Well, when you understand that this is Intel’s answer to solid state drives (SSD) based on reduced cost; shorter time to market; leveraging existing JEDEC package designs and test infrastucture; known reliability issues…. you realize that it is actually extremely cool, very pragmatic and a perfect example of perfecting a known form, rather than waiting for the next new thing to be half-ready. I’ve got to confess: I saw something similar stacked, one on top of the other (using PoP paste), by an Asian customer and thought it was a joke. It’s not. Saeed told us his team was going to be using 8 stacked 4GB die initially, moving to 8GB by next year. PoP stack two of these and that makes 128GB (0.128TB) of solid state drive. Nice! How about the access speed, though?
- Implementation of 0.3mm WLP (wafer level packaging) is two years away… and always will be. Here’s the background: Jan Vardaman of TechSearch International took a novel approach to her chairmanship of a panel of industry luminaries discussing the future of WLP. She gave a homework preassignment to her four experts (from Broadcom, Qualcomm, Casio and National Semiconductor). There were a lot of common themes in their responses, and the general agreement was that it looks like 0.3mm WLP is easily feasible and has been for years, but it’s the substrate guys who can not reduce the routing costs to make 0.3mm feasible for portable applications. There may be 0.32 or 0.35mm as interim measures for mobile consumer applications, however, but that could be the limit based on costs.
- Rosalia Beica of Applied Materials gave the closing speech, talking about the work done by the EMC-3D group. Basically, the EMC-3D group has the technology and Applied has the tools to copper-fill diffusion-barrier-layer-coated 20:1 aspect ratio silicon apertures (20microns deep, for the record), eliminating issues with voiding and overburden. Now the question is: will copper be the conductive via-fill material of choice? Thermal cycling does seem to put a lot of stress inside the vias from the modeling work I’ve seen. Let’s see how this pads out.
- No news that wafer-thinning will be critical for wafer-stacking, but we heard from Bill Crouch of Süss Microtec that current minimum die thicknesses are 10microns for logic, 40microns for DRAM and 25microns for flash. The critical yield issue for thinned wafers remains debonding at the wafer edges without cracking, with the key being the physical properties of the temporary waferbonding adhesive.
- Finally: too many pennants and “you look like a Russian General” as one wag told me. He’s right. Actually I’m not sure “pennant” is the correct name for those sticky “badges of honor” that the SMTA puts on the bottom of your lanyard name badge, but yes, I did look a bit of a pillock [see picture below].
Quick reminder: Device-in-skull is one year closer - the technology is already appearing.
Cheers! See you all next year. Andy